1. Technical Field
This disclosure relates to analog-to-digital converters, and more particularly, to circuitry and methodology for sampling an analog input signal with reduced average input current during an analog-to-digital conversion process. Furthermore this disclosure relates to circuitry and methodology for sampling an analog input signal with reduced average input current and reference current during an analog-to-digital conversion process.
2. Background Art
A typical analog-to-digital converter samples an analog input signal in order to convert it into a corresponding digital signal. During this process, the converter loads the input signal and modifies it depending upon the impedance of the signal source. Such a modification directly influences the accuracy of the conversion process and the final result. For slower-speed and lower-resolution converters, errors caused by the input signal modification are insignificant and may be safely ignored.
On the other hand, recent developments in sensor technology, improvements in converter resolution and converter speed have made such errors significant factors limiting further increase in conversion accuracy. Moreover, the tendency to reduce power consumption and the expansion of portable applications has spread the use of a variety of sensors with relatively high source impedances. Examples of such sensors are high-value resistive bridges used to monitor weight and pressure.
At the same time, the development of over-sampling converter technology has pushed resolution of analog-to-digital conversion to a 24-bit level and higher. Typical over-sampling converters use switched-capacitor front end circuits including one or more sampling capacitors to sample an analog input signal multiple times for each conversion cycle. During each sampling process, a certain amount of charge is transferred between the signal source and the converter front end capacitors resulting in an equivalent input current flow. As this input current passes through the signal source impedance it causes a voltage change, modifying the original input value and creating a sampling error.
The value of the input current is directly proportional to the size of the sampling capacitors and to the sampling rate. Due to thermal noise limitations an increase in the conversion resolution requires a substantial increase in the size of the sampling capacitors resulting in the corresponding increase in the input current. At the same time, any increase in the overall conversion rate causes a proportional increase in the input signal sampling rate, resulting in proportional increased input current.
Two different strategies are typically used to deal with this problem. The first approach is to guarantee the complete settling (within the accuracy of the converter) of the front end sampling circuit including the input signal source impedance. This is a very difficult goal to achieve and it rapidly becomes impractical as the desired conversion accuracy and speed increase. The source impedance of a sensor imposes a theoretical limit on available ranges of conversion speed and resolution. Unavoidable parasitic capacitors and necessary signal filter capacitors involved in practical configurations further limit these ranges. An example of this approach is the LTC® 2410 analog-to-digital converter developed by Linear Technology Corporation, assignee of the present subject matter.
The second approach uses isolation buffers and amplifiers interposed between the sensor and the converter. Such buffers can be external to the converter or may be integrated within the converter front end sampling circuits. Configurations using external buffers offer great flexibility but place an unacceptable heavy burden upon the user in order to maintain the global accuracy of the measurement chain. These configurations also demand supplemental power supply rails, critical power supply sequencing circuits and additional physical space. Integrating the buffers within the converter front end sampling circuits partially resolves these issues. Nevertheless, the integrated buffers limit the analog-to-digital converter overall accuracy and dynamic range. An example of this approach is the LTC® 2442 analog-to-digital converter developed by Linear Technology Corporation, assignee of the present subject matter.
Furthermore, in many practical applications the analog-to-digital converter reference signals are also generated by relatively high source impedance sensors utilized in ratiometric fashion. Current taken by the analog-to-digital converter from the reference source during the conversion process passes through this source impedance creating a conversion error. Traditionally this problem has been resolved by using external reference buffer circuits or by limiting the reference signal source impedance. The first approach severely limits the conversion result accuracy and repeatability while the second places unreasonable restrictions upon the analog-to-digital converter range of applications.
Therefore, there is a need for a new sampling technique to reduce an average input current and an average reference current caused by the charge taken from an input signal source and a reference signal source during an analog-to-digital conversion process. A copending application No. 11/253,082, filed on Oct. 17, 2005, entitled “SYSTEM AND METHOD FOR SAMPLING ANALOG INPUT SIGNAL TO REDUCE AVERAGE DIFFERENTIAL INPUT CURRENT” and incorporated herewith by reference, discloses a differential front-end sampling circuit that reduces an average differential input current. However, the differential sampling circuit is not able to substantially reduce an average common-mode input current which may create uncompensated conversion errors through unbalanced source resistance present at two nodes of the input signal source.
As the average common mode input current significantly influences the accuracy of an analog-to-digital conversion system, it would be desirable to provide a sampling arrangement for reducing the average input current. Furthermore it is highly desirable to provide a sampling arrangement for reducing the average reference current.